Recently, miniaturization of semiconductors has progressed, and attempts are being made to use, as a material for gate insulating films of transistors or for capacitive films of DRAMs, dielectric materials with a higher dielectric constant instead of, for example, silicon oxide that has been conventionally used. In addition, ferroelectric memories provided with ferroelectric films for memory capacitors in memory cells have been put into practical use as new nonvolatile memories.
High-dielectric-constant or ferroelectric films used for the semiconductor devices have been conventionally formed by the following manner. First, as an underlying layer, a film having a crystal orientation is formed over a substrate. Next, a high-dielectric-constant or ferroelectric film is deposited by a process such as a sputtering process or a chemical vapor deposition process using an organic metal complex (an MOCVD process). In this case, to obtain a film with high crystallinity, a substrate temperature is kept at 650° C. or more during the deposition, or heat treatment is performed at 650° C. or more inside, for example, a furnace for high-speed lamp heating after the deposition has been performed. Subsequently, a metal film for use in an upper electrode is formed.
In recent years, portable information terminal units driven by batteries are widely used. In such units, there is a strong demand for reducing the power supply voltage without compromising high-speed operations in order to prolong the battery lifetime. Reducing the threshold voltage is effective in realizing high-speed operations even in low power supply voltages. In this case, however, the leakage current occurring when the gate is off becomes large, so that there should be a lower limit to the threshold voltage. In view of this, instead of the silicon oxide films conventionally used, the use of a high-dielectric-constant film or improvement in structure of the device itself has been proposed.
As a device that can solve this problem and has a small leakage current at a low voltage and high driving force, a device called DTMOS device (Dynamic Threshold Voltage MOSFET) has been proposed, as disclosed in, for example, a literature “A Dynamic Threshold Voltage MOSFET (DTMOS device) for Ultra-Low Voltage Operation”, by F. Assaderaghi et. al., IEDM94 Ext. Abst. P.809.
FIG. 21 is a cross-sectional view showing a structure of the known DTMOS device proposed in the literature. As shown in FIG. 21, the known DTMOS is composed of an n-DTMOS device and a p-DTMOS device. Each of the n- and p-DTMOS devices includes: a gate insulating film provided on an active region of a semiconductor substrate; a gate electrode; source/drain regions defined in parts of the active region and located to the right- and left-hand sides of the gate, respectively, (i.e., n-type regions in the n-DTMOS device and p-type regions in the p-DTMOS device); and a substrate region that is the part of the active region except for the source/drain regions (a p+ Si layer in the n-DTMOS device and an n+ Si layer in the p-DTMOS device). Part of the substrate region directly below the gate insulating film is a channel region. The substrate region (a body region) and the gate electrode are connected to be electrically short-circuited via an interconnection. In the structure shown in FIG. 21, an SOI substrate is used, and thus a buried oxide film is formed under the active region.
Application of a bias voltage to the gate with the gate and the body being short-circuited as described above allows a forward bias voltage that is equal to the gate bias voltage to be applied to the channel region via the body. With this application, the same state as in a normal MOS transistor is created when the gate bias is off, and the body is forwardly biased with increase in the gate bias voltage when the gate bias is on, thereby decreasing the threshold voltage.
When the gate bias is off, the leakage current in such a DTMOS device is equal to the leakage current in a normal MOS transistor formed on an SOI substrate (i.e., a transistor in which the gate and the body are not short-circuited). On the other hand, when the gate bias is on, the threshold voltage decreases as described above. Thus, the gate overdrive effect improves, thereby significantly enhancing the driving force. In addition, since there is almost no potential difference between the gate and the channel region in the DTMOS device, a vertical electric field on the surface of the substrate becomes extremely smaller than that in the normal transistor. As a result, deterioration in carrier mobility due to increase in the vertical electric field is suppressed so that the driving force is remarkably enhanced.
Therefore, the DTMOS device functions as a transistor that can operate at high speed with a low threshold voltage, i.e., a low power supply voltage, in part of the operating voltage range before a lateral parasitic bipolar transistor, which occurs among the n-type gate, p-type body (a base) and n-type source/drain regions (an emitter and a corrector), is on and causes the body current to increase to a problematic extent in practice. In addition, the DTMOS device that has substantially the same structure as that of a normal MOS device can be fabricated easily through substantially the same number of fabrication steps as that for the normal MOS device.